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Sorted By: Year ascending |
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2018 |
Philippos Papaphilippou, Wayne Luk |
Accelerating Database Systems Using FPGAs: A Survey 2018 28th International Conference on Field Programmable Logic and Applications (FPL). DOI: http://dx.doi.org/10.1109/fpl.2018.00030 |
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2018 |
Philippos Papaphilippou, Chris Brooks, Wayne Luk |
FLiMS: Fast Lightweight Merge Sorter 2018 International Conference on Field-Programmable Technology (FPT). DOI: http://dx.doi.org/10.1109/fpt.2018.00022 |
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2019 |
Stefan Krieg, Thomas Luu, Johann Ostmeyer, Philippos Papaphilippou, Carsten Urbach |
Accelerating Hybrid Monte Carlo simulations of the Hubbard model on the hexagonal lattice Computer Physics Communications, 236, pp15--25. DOI: http://dx.doi.org/10.1016/j.cpc.2018.10.008 |
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2019 |
Philippos Papaphilippou, Holger Pirk, Wayne Luk |
Accelerating the Merge Phase of Sort-Merge Join 2019 29th International Conference on Field Programmable Logic and Applications (FPL). DOI: http://dx.doi.org/10.1109/fpl.2019.00025 |
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2019 |
Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk |
Pangloss: a novel Markov chain prefetcher The Third Data Prefetching Championship (DPC3), held in conjunction with ISCA 2019 |
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2020 |
Philippos Papaphilippou, Chris Brooks, Wayne Luk |
An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics 2020 30th International Conference on Field-Programmable Logic and Applications (FPL). DOI: http://dx.doi.org/10.1109/fpl50879.2020.00021 |
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2020 |
Philippos Papaphilippou, Jiuxi Meng, Wayne Luk |
High-Performance FPGA Network Switch Architecture Proceedings of the 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays. DOI: http://dx.doi.org/10.1145/3373087.3375299 |
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2021 |
Philippos Papaphilippou and Paul H. J. Kelly and Wayne Luk |
Demonstrating custom SIMD instruction development for a RISC-V softcore 2021 31st International Conference on Field-Programmable Logic and Applications (FPL). DOI: http://dx.doi.org/10.1109/fpl53798.2021.00030 |
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2021 |
Philippos Papaphilippou and Kelly Paul H. J. and Wayne Luk |
Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions 2021 31st International Conference on Field-Programmable Logic and Applications (FPL). DOI: http://dx.doi.org/10.1109/fpl53798.2021.00082 |
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2021 |
Papaphilippou, Philippos |
Reconfigurable acceleration of big data analytics Imperial College London. DOI: http://dx.doi.org/10.25560/94446 |
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2021 |
Philippos Papaphilippou and Kentaro Sano and Boma A. Adhi and Wayne Luk |
Efficient Queue-Balancing Switch for FPGAs 2021 International Conference on Field-Programmable Technology (ICFPT). DOI: http://dx.doi.org/10.1109/icfpt52863.2021.9609867 |
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2021 |
Philippos Papaphilippou and Jiuxi Meng and Nadeen Gebara and Wayne Luk |
Hipernetch: High-Performance FPGA Network Switch ACM Transactions on Reconfigurable Technology and Systems, 15(1), pp1--31. DOI: http://dx.doi.org/10.1145/3477054 |
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2021 |
Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk |
Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions Fifth Workshop on Computer Architecture Research with RISC-V (CARRV 2021), co-located with ISCA 2021 |
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2022 |
Philippos Papaphilippou and Wayne Luk and Chris Brooks |
FLiMS: a Fast Lightweight 2-way Merger for Sorting IEEE Transactions on Computers. DOI: http://dx.doi.org/10.1109/tc.2022.3146509 |
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2022 |
Philippos Papaphilippou, Myrtle Shah |
FPGA-extended General Purpose Computer Architecture The 18th International Symposium on Applied Reconfigurable Computing (ARC). DOI: http://dx.doi.org/10.48550/ARXIV.2203.10359 |
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2023 |
Papaphilippou, Philippos, Sano, Kentaro, Adhi, Boma A., Luk, Wayne |
Experimental survey of FPGA-based monolithic switches and a novel queue balancer IEEE Transactions on Parallel and Distributed Systems. DOI: http://dx.doi.org/10.1109/TPDS.2023.3244589 |
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2023 |
Philippos Papaphilippou,Zhiqiang Que, Wayne Luk |
Efficiently Removing Sparsity for High-Throughput Stream Processing The International Conference on Field-Programmable Technology (FPT) 2023 |
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2024 |
Philippos Papaphilippou, Thiem Van Chu |
Efficient deadlock avoidance for 2D mesh NoCs that use OQ or VOQ routers IEEE Transactions on Computers, pp13 |
